The latch-up phenomenon creates an inrush current related to the triggering of a parasitic thyristor structure inherent to some integrated circuit technologies, and particularly CMOS type technologies.
In addition to MOS active transistors, there are several parasitic bipolar transistors in the circuit for which the gain may be very high (50 to 100). Therefore, they do not create a nuisance for operation of the circuit, except in some parasitic thyristor type configurations (PNPN) in which two parasitic bipolar transistors work in positive inverse feedback, forming a bistable configuration that can be triggered by small disturbances. Once the inverse feedback has been set up, the thyristor is in a strongly on-state that is self-powered even after the disturbance has disappeared, and can be destructive for the circuit.
This type of parasitic thyristor configuration is illustrated in FIG. 1 that shows a section view through the structure of a cell in an integrated CMOS circuit, for example including a logical gate such as an inverter, and FIG. 2 shows the equivalent connection circuit of the parasitic thyristor.
The cell in the CMOS circuit shown on FIG. 1 of the type with a P substrate and an N well comprises two P and N MOS transistors, made in a P− doped semiconducting substrate 1, the P MOS transistor being formed in an N− doped region 2 (well) of the substrate including two P+ doped regions 3, 4 delimiting the channel of the P MOS transistor, the first being connected to the power supply terminal Vdd and the second to the circuit output, and an N+ doped region 5 also connected to the terminal Vdd and being connected to the power supply polarization. The N MOS transistor is composed of two N+ doped regions 7, 8 delimiting a channel formed in the substrate 1, one being connected to the ground terminal Vss and the other to the output of the circuit, and of a P+ doped region 6 at the output from the circuit also connected to the terminal Vss and to which the ground polarization is connected.
The gates of these transistors are composed of polysilicon layers 9 connected to the input of the circuit and formed at a distance from and facing the n and p channels of the two transistors.
FIG. 1 also shows the layout of the parasitic thyristor with respect to the doped regions forming the two MOS transistors. As illustrated in FIGS. 1 and 2, the parasitic thyristor is formed by two bipolar transistors, one pnp type transistor T1 and one npn type transistor T2 mounted head-foot, the collector of one being connected to the base of the other, while the emitters of these two transistors are connected to the Vdd and Vss terminals of the circuit respectively. The emitter-base junction of transistor T1 is formed by the association of the P+ doped region 4 and N− doped region 2, while the collector-base junction of this transistor is formed by the association of the P− doped substrate 1 and the N− doped region 2. Therefore the emitter and the base of transistor T1 are connected to the Vdd terminal of the circuit, the emitter being connected directly and the base being connected through a resistance RN− representing the resistance of the well 2. The base-emitter junction of the transistor T2 is formed by the association of the substrate 1 and the N+ doped region 7 connected to the Vss terminal of the circuit, while the base-collector junction of this transistor is formed by the association of the substrate 1 and the region 2. Therefore the base and the emitter of the transistor T2 are connected to the Vss terminal of the circuit, the base being connected directly and the emitter being connected through a resistance RP− representing the resistance of the substrate 1.
The parasitic thyristor can be triggered by an overvoltage on the circuit power supply, a current injection on an input or output pin of the integrated circuit, or by radiation of particles. This triggering produces a strong inrush current between the power supply pins of the integrated circuit that usually causes destruction of the circuit.
The sensitivity of an integrated circuit to the latch-on phenomenon can be measured by injecting a current into an input or output pin of the integrated circuit when the circuit is powered normally, by detecting a current overconsumption on the power supply that may be more or less sudden, and by measuring the intensity of the injected current to the appearance of the overconsumption. If the detected overconsumption ceases with the current injection, the latch-on phenomenon is said to be temporary. However, if the overconsumption remains even after the current injection has stopped, the latch-on phenomenon is said to be permanent. A circuit is considered to be only slightly sensitive to this phenomenon if it is only temporary or if the permanent latch-on phenomenon only appears with an injected current with a high intensity (typically more than 100 mA for a CMOS circuit).
There are several techniques for reducing the sensitivity of components to the locking phenomenon.
A first technique consists of using in-depth epitaxied substrates (in other words strongly doped substrates) so as to reduce the base resistance of one of the two transistors, and in this case the base resistance RP− of transistor T2 forming the parasitic thyristor. The base resistance of the transistors T1, T2 can also be reduced using strongly doped wells made in-depth in the substrate. FIG. 3 shows a sectional view through the structure of a CMOS integrated circuit and illustrates the epitaxied substrate technique used to obtain in-depth layers 11, 12 with low resistivity.
These techniques are expensive to implement because they require that a large number (between 5 and 10) of component manufacturing masks should be modified.
Particular routing rules have also been implemented to reduce the sensitivity of components to the latch-on phenomenon, to reduce the values of the base resistances RN− and RP− of the two transistors T1 and T2. This technique is illustrated on FIG. 4 that shows a top view of the CMOS circuit shown on FIG. 1. On FIG. 4, the circuit comprises metallization lines 15, 17 and 18 that also transport the voltage Vdd, the input signal and the voltage Vss respectively, and a metallization segment 10 connecting the drains (regions 4 and 7) of the two MOS transistors. The lines 15 and 18 each comprise an arm 16, 19 designed to carry the voltage Vdd to the polarization region 5, and the voltage Vss to the polarization region 6. The input metallization line 17 is connected to the polysilicon line 9 forming the transistors gate.
The arms 16 and 19 are also connected to regions 4 and 7 respectively forming the sources of the MOS transistors that are also connected to potentials Vdd and Vss respectively, and firstly regions 4 and 5, and secondly regions 6 and 7 are arranged as close as possible to each other, to reduce the values of the base resistances RN− and RP− of the two transistors T1 and T2. These arrangements reduce the base resistances RN− and RP−, to a few tens or a few hundreds of ohms.
However, these routing rules are not infallible, and even if the well and substrate connections are correctly positioned, current levels injected during the latch-on test (typically 100 mA) are sometimes sufficient to reach the polarization voltage (0.6 V) of the emitter-base junctions of the parasitic thyristor directly. This voltage can sometimes be reached with resistances of a few hundred ohms with a substrate current of a few mA.